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Guide: add a diagram for Inclusion Pipeline & Approval Subsystem (#1457)
* guide: optimize diagrams for readability * guide: inclusion subsystem diagram * guide: rename Approval Subsystem for clarity * guide: correct the approval subsystem * guide: clarify that validator are selected from the same set * guide: simplify secondary checkers labels
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Andronik Ordian
@@ -56,19 +56,109 @@ Reiterating the lifecycle of a candidate:
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1. Included: Backed and considered available.
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1. Included: Backed and considered available.
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1. Accepted: Backed, available, and undisputed
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1. Accepted: Backed, available, and undisputed
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> TODO Diagram: Inclusion Pipeline & Approval Subsystems interaction
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```dot process Inclusion Pipeline
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digraph {
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subgraph cluster_vg {
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label=<
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Parachain Validators
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<br/>
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(subset of all)
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>
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labeljust=l
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style=filled
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color=lightgrey
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node [style=filled color=white]
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v1 [label="Validator 1"]
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v2 [label="Validator 2"]
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v3 [label="Validator 3"]
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b [label="(3) Backable", shape=box]
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v1 -> v2 [label="(2) Seconded"]
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v1 -> v3 [label="(2) Seconded"]
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v2 -> b [style=dashed arrowhead=none]
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v3 -> b [style=dashed arrowhead=none]
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v1 -> b [style=dashed arrowhead=none]
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}
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v4 [label=<
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<b>Validator 4</b> (relay chain)
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<br/>
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<font point-size="10">
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(selected by BABE)
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</font>
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>]
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col [label="Collator"]
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pa [label="(5) Relay Block (Pending Availability)", shape=box]
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pb [label="Parablock", shape=box]
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rc [label="Relay Chain Validators"]
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subgraph cluster_approval {
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label=<
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Secondary Checkers
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<br/>
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(subset of all)
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>
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labeljust=l
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style=filled
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color=lightgrey
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node [style=filled color=white]
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a5 [label="Validator 5"]
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a6 [label="Validator 6"]
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a7 [label="Validator 7"]
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}
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b -> v4 [label="(4) Backed"]
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col -> v1 [label="(1) Candidate"]
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v4 -> pa
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pa -> pb [label="(6) a few blocks later..." arrowhead=none]
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pb -> a5
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pb -> a6
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pb -> a7
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a5 -> rc [label="(7) Approved"]
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a6 -> rc [label="(7) Approved"]
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a7 -> rc [label="(7) Approved"]
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}
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```
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The diagram above shows the happy path of a block from (1) Candidate to the (7) Approved state.
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It is also important to take note of the fact that the relay-chain is extended by BABE, which is a forkful algorithm. That means that different block authors can be chosen at the same time, and may not be building on the same block parent. Furthermore, the set of validators is not fixed, nor is the set of parachains. And even with the same set of validators and parachains, the validators' assignments to parachains is flexible. This means that the architecture proposed in the next chapters must deal with the variability and multiplicity of the network state.
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It is also important to take note of the fact that the relay-chain is extended by BABE, which is a forkful algorithm. That means that different block authors can be chosen at the same time, and may not be building on the same block parent. Furthermore, the set of validators is not fixed, nor is the set of parachains. And even with the same set of validators and parachains, the validators' assignments to parachains is flexible. This means that the architecture proposed in the next chapters must deal with the variability and multiplicity of the network state.
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```dot process
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```dot process
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digraph {
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digraph {
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rca [label = "Relay Block A" shape=rectangle]
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rca [label="Relay Block A" shape=box]
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rcb [label = "Relay Block B" shape=rectangle]
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rcb [label="Relay Block B" shape=box]
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rcc [label = "Relay Block C" shape=rectangle]
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rcc [label="Relay Block C" shape=box]
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vg1 [label =<<b>Validator Group 1</b><br/><br/><font point-size="10">(Validator 4)<br/>(Validator 1) (Validator 2)<br/>(Validator 5)</font>>]
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vg1 [label=<
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vg2 [label =<<b>Validator Group 2</b><br/><br/><font point-size="10">(Validator 7)<br/>(Validator 3) (Validator 6)</font>>]
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<b>Validator Group 1</b>
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<br/>
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<br/>
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<font point-size="10">
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(Validator 4)
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<br/>
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(Validator 1) (Validator 2)
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<br/>
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(Validator 5)
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</font>
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>]
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vg2 [label=<
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<b>Validator Group 2</b>
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<br/>
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<br/>
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<font point-size="10">
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(Validator 7)
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<br/>
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(Validator 3) (Validator 6)
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</font>
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>]
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rcb -> rca
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rcb -> rca
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rcc -> rcb
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rcc -> rcb
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@@ -82,23 +172,46 @@ In this example, group 1 has received block C while the others have not due to n
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```dot process
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```dot process
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digraph {
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digraph {
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rca [label = "Relay Block A" shape=rectangle]
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rca [label="Relay Block A" shape=box]
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rcb [label = "Relay Block B" shape=rectangle]
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rcb [label="Relay Block B" shape=box]
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rcc [label = "Relay Block C" shape=rectangle]
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rcc [label="Relay Block C" shape=box]
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rcc_prime [label = "Relay Block C'" shape=rectangle]
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rcc_prime [label="Relay Block C'" shape=box]
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vg1 [label =<<b>Validator Group 1</b><br/><br/><font point-size="10">(Validator 4) (Validator 1)</font>>]
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vg1 [label=<
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vg2 [label =<<b>Validator Group 2</b><br/><br/><font point-size="10">(Validator 7) (Validator 6)</font>>]
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<b>Validator Group 1</b>
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vg3 [label =<<b>Validator Group 3</b><br/><br/><font point-size="10">(Validator 2) (Validator 3)<br/>(Validator 5)</font>>]
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<br/>
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<br/>
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<font point-size="10">
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(Validator 4) (Validator 1)
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</font>
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>]
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vg2 [label=<
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<b>Validator Group 2</b>
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<br/>
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<br/>
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<font point-size="10">
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(Validator 7) (Validator 6)
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</font>
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>]
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vg3 [label=<
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<b>Validator Group 3</b>
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<br/>
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<br/>
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<font point-size="10">
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(Validator 2) (Validator 3)
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<br/>
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(Validator 5)
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</font>
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>]
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rcb -> rca
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rcb -> rca
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rcc -> rcb
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rcc -> rcb
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rcc_prime -> rcb
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rcc_prime -> rcb
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vg1 -> rcc [style=dashed arrowhead=none]
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vg1 -> rcc [style=dashed arrowhead=none]
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vg2 -> rcc_prime [style=dashed arrowhead=none]
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vg2 -> rcc_prime [style=dashed arrowhead=none]
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vg3 -> rcc_prime [style=dashed arrowhead=none]
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vg3 -> rcc_prime [style=dashed arrowhead=none]
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vg3 -> rcc [style=dashed arrowhead=none]
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vg3 -> rcc [style=dashed arrowhead=none]
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}
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}
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```
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```
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