Update LLVM 22 to ca0698598261 and remove LLVM patches (#510)

Co-authored-by: LJ <81748770+elle-j@users.noreply.github.com>

CHANGELOG.md

@@ -3,7 +3,10 @@
 ## Unreleased
 
 - Supported `polkadot-sdk` rev: `2603`
-- Updated `LLVM` from `21.1.8` to LLVM `22.1.3`
+
+### Changed
+
+- Updated `LLVM` from `21.1.8` to LLVM `22.1.4`
 
 ## v1.1.0
 

patches/llvm/llvm-pr-163679.patch

@@ -1,15 +0,0 @@
-diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
-index eb875583ff..169465e18f 100644
---- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
-+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
-@@ -24830,7 +24830,8 @@ bool RISCVTargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
-   // instruction, as it is usually smaller than the alternative sequence.
-   // TODO: Add vector division?
-   bool OptSize = Attr.hasFnAttr(Attribute::MinSize);
--  return OptSize && !VT.isVector();
-+  return OptSize && !VT.isVector() &&
-+         VT.getSizeInBits() <= getMaxDivRemBitWidthSupported();
- }
- 
- bool RISCVTargetLowering::preferScalarizeSplat(SDNode *N) const {
-

patches/llvm/llvm-pr-190219.patch

@@ -1,18 +0,0 @@
-diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
-index e0597988e..56520d911 100644
---- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
-+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
-@@ -11055,10 +11055,10 @@ void TargetLowering::forceExpandMultiply(SelectionDAG &DAG, const SDLoc &dl,
-   // If HiLHS and HiRHS are set, multiply them by the opposite low part and add
-   // the products to Hi.
-   if (HiLHS) {
-+    SDValue RHLL = DAG.getNode(ISD::MUL, dl, VT, HiRHS, LHS);
-+    SDValue RLLH = DAG.getNode(ISD::MUL, dl, VT, RHS, HiLHS);
-     Hi = DAG.getNode(ISD::ADD, dl, VT, Hi,
--                     DAG.getNode(ISD::ADD, dl, VT,
--                                 DAG.getNode(ISD::MUL, dl, VT, HiRHS, LHS),
--                                 DAG.getNode(ISD::MUL, dl, VT, RHS, HiLHS)));
-+                     DAG.getNode(ISD::ADD, dl, VT, RHLL, RLLH));
-   }
- }
-